1. Field of the Invention
The present invention relates to a microcomputer, particularly to a bus use request adjusting apparatus for a plurality of data processors including a CPU, direct memory access unit (hereafter referred to as DMA processor) in the microcomputer to output a bus use request.
2. Description of the Prior Art
FIG. 14 is a block diagram of a microcomputer system using a bus use request adjusting apparatus according to the prior art. In FIG. 14, symbol 1 is a CPU (central processing unit), 2 is an interrupt control unit (ICU) for adjusting interrupt request signals INT0 and INT1 outputted from peripheral units and sending an interrupt request to the CPU 1, and 3 is a DMA process (DMA) for adjusting direct memory access (hereafter referred to as DMA) request signals DMAR0 and DMAR1 outputted from peripheral units. Symbol 4 is an address bus and 5 is a data bus. Memory units and peripheral units such as DRAM and ROM, though not illustrated in FIG. 14, are connected with the microcomputer system by the address bus 4 and data bus 5. Symbol 6 is a refresh control unit (REF) for refreshing the DRAM, which stores a counter to obtain a refresh time interval. Symbol 7 is a synchronous clock generator (CLK) for generating a synchronous clock of the CPU 1. Symbol 8 is a bus use request adjusting apparatus for adjusting a bus use request of the DMA processor 3, an external bus use request (hereafter referred to as a hold request), and a bus use request of the refresh control unit 6, in which symbol 129 shows a system synchronizing signal .phi. and which stores a selection circuit to be mentioned later.
Symbol 9 is a signal line for inputting a signal BUSY indicating that the CPU 1 is busy to the bus use request adjusting apparatus 8, 10 is a signal line for inputting a bus use request signal BRQDMA of the DMA processor (SMA) 3 to the bus use request adjusting apparatus 8, 11 is a signal line for inputting a signal DMSC indicating a breakpoint for DMA transfer to the bus use request adjusting apparatus 8, 12 is a signal line for inputting a signal HOLD indicating a hold request to the bus use request adjusting apparatus 8, 13 is a signal line for inputting a bus use request signal BRQREF of the refresh control unit (REF) 6 to the bus use request adjusting apparatus 8, and 14 is a signal line for inputting a signal REFE indicating the end of refresh to the bus use request adjusting apparatus 8.
Symbol 15 is a signal line for inputting a bus use permission signal CPUST for the CPU 1 from the bus use request adjusting apparatus 8 to the CPU 1, 16 is a signal line for inputting a bus use permission signal DMAST for the DMA processor (DMA) 3 from the bus use request adjusting apparatus 8 to the DMA process (DMA) 3, 17 is a signal line for outputting a response signal HOLDA for a hold request, 18 is a signal line for inputting a bus use permission signal REFST for the refresh control unit (REF) 6 from the bus use request adjusting apparatus 8 to the refresh control unit (REF) 6. Symbol 19 is a signal line for inputting a signal RDY for inhibiting generation of a synchronous clock from the bus use request adjusting apparatus 8 to the synchronous clock generation circuit 7, and 20 is a signal line for inputting a CPU synchronous clock .phi. CPU from the synchronous clock generation circuit 7 to the CPU 1.
FIG. 15 is a block diagram of a selection circuit 8a in the bus use request adjusting apparatus 8 according to the prior art for deciding a unit to which bus use permission is assigned when a bus use request from the DMA processor (DMA) 3 and the hold request and refresh control unit (RE) 6 are completed. In FIG. 15, symbols 21, 22, and 23 are input terminals for the bus use request signal BRQDMA, signal HOLD, and bus use request signal BRQREF respectively, and symbols 24, 25, 26, and 27 are output terminals for the bus use permission signal CPUST, bus use permission signal DMAST, response signal HOLDA, and signal REFST. Symbol 28 is a logic gate which outputs the logic "1" only when the logic "0" is inputted from every terminal with a circle "O". Symbols 29 and 30 are logic gates which output the logic "1" only when the logic "1" is inputted from terminals with no circle "O" and the logic "0" is inputted from those with a circle "O". Symbols 31, 32, 33, and 34 are latch circuits which hold input data for a bus use request at the rise of a pulse SAMP indicating the end of bus use to be generated when the CPU 1 does not use any bus if bus use permission is assigned to the CPU 1 or at the breakpoint for DMA transfer if bus use permission is assigned to the DMA processor (DMA) 3, or when the signal HOLD comes to the logic "0" under the bus release state by the hold request or at the end of refresh if bus use permission is assigned to the refresh control unit (REF) 6. In this case, the pulse SAMP is a signal which indicates that bus use ends at the present and comes to "1" when the synchronous clock .phi. is "1" at the end of refresh, where the CPU 1 does not use any bus and at the breakpoint for DMA transfer or where the signal HOLD comes to the logic "1" under the bus release state by the hold request.
Moreover, for the selection circuit 8a, priority is given to the bus use request BRQDMA, signal HOLD, and bus use request signal BRQREF by the logic gates 29 and 30, in which the signal HOLD is prior to the bus use request signal BRQDMA and the bus use request signal BRQREF is prior to the signal HOLD. According to the priority, only one signal is selected even if two or more signals among the bus use request signal BRQDMA, signal HOLD, and bus use request signal BRQREF are inputted. If no signal is inputted (three inputs are "0"), the bus use request signal CPUST of the CPU 1 is resultingly synthesized by the logic gate 28.
The operation according to the prior art is described below by referring to FIGS. 14 and 16. FIG. 16 is a timing chart showing the operation of the above microcomputer system. In FIG. 16, symbol 35 is a synchronous clock .phi., 36 is a signal E (reverse) which is generated by the CPU 1 and comes to the logic "0" when data in the data bus is valid, 37 is a signal RDYCPU (reverse) which is an internal signal of the synchronous clock generator (CLK) 7 and comes to the logic "0" when stopping the synchronous clock .phi. CPU for the CPU 1, and 38 shows the state of the pulse SAMP. In this case, the synchronous clock .phi. is different from the CPU synchronous clock .phi. cpu. When the system operates, the signal RDY is not always outputted to the signal line 19 but the synchronous clock generator 7 generates the synchronous clock .phi.. That is, the CPU synchronous clock .phi. cpu is a signal produced from the synchronous clock .phi. and the signal RDYCPU (reverse) by the synchronous clock generator (CLK) 7, which is kept at "0" while the signal DYCPU (reverse) equals "0". Symbol 39 is a DMA signal DMAR0 and 40 shows the state of the bus use request signal BRQDMA. Symbol 41 is a signal OVF which is outputted by a counter stored in the refresh control unit (REF) 6 and comes to the logic "1" when the counter overflows and 42 shows the state of the bus use request signal BRQREF. Symbol 43 shows the state of the signal HOLD. Symbol 44 shows the units {CPU 1, DMA processor (DMA) 3, and refresh control unit (REF) 6} which receive bus use permission at each time and 45 shows an address in the address bus 4 corresponding to an operational state of each unit.
In this case, it is assumed that the DMA process (DMA) 3 is set so as to perform DMA transfer twice under the burst state when receiving the DMA signal DMAR0. At the time of T1, the DMA signal DMAR0 is inputted to the DMA processor (DMA) 3 from an external unit (symbol 39 in FIG. 16). Then, the DMA processor (DMA) 3 causes the bus use request signal BRQDMA to rise at the time of T2 (symbol 40 in FIG. 16). When the pulse SAMP rises at the time of T3, the bus use permission signal DMAST is outputted from the selection circuit 8a (symbols 38, 40, 42, and 43 in FIG. 16) because signals at the logic "0" are the signal HOLD and the bus use request signal BRQREF and a signal at the logic "1" is only the bus use request signal BRQDMA. Therefore, the DMA processor (DMA) 3 obtains the bus use right to start DMA transfer. The address bus states DMA (source) and DMA (destination) at the times of T4 and T5 shows that the transfer-source address and transfer-destination address in DMA transfer are outputted to the address bus. DMA (idle) shown in FIG. 16 is the state in which the DMA process performs internal processings using no bus (symbol 45 in FIG. 16).
At the time of T6 where the counter stored in REF 6 overflows and the signal OVF indicating that the DRAM refresh time expires rises, the refresh control unit (REF) 6 causes the signal BRQREF to rise at the time of T7 (symbols 41 and 42 in FIG. 16). When the pulse SAMP rises at the time of T8, signals at the logic "1" are the bus use request signal BRQDMA and bus use request signal BRQREF among the bus use request signal BRQDMA, signal HOLD, and bus use request signal BRQREF (symbols 38, 40, and 42 in FIG. 16). Therefore, the bus use permission signal REFST (FIG. 15) is outputted from the selection circuit according to the above priority. Thereby, the refresh control unit (REF) 6 obtains the bus use right to start the refresh of DRAM (not illustrated). However, because DMA transfer has not terminated yet, the bus use request signal BRQDMA is kept at the logic "1" even during the refresh.
When the refresh terminates at the time of T9, the pulse SAMP rises (symbol 38 in FIG. 16). At this point of time, a signal at the logic "1" is only the bus use request signal BRQDMA among the bus use request BRQDMA, signal HOLD, and bus use request signal BRQREF. Therefore, the DMA process (DMA) 3 obtains the bus use right to restart DMA transfer which has been interrupted (symbols 40, 42, and 43 in FIG. 16).
When DMA transfer terminates at the time of T10, the pulse SAMP rises (symbol 38 in FIG. 16). At this point of time, the CPU 1 obtains the bus use right because the bus use request signal BRQDMA, signal HOLD, and bus use request signal BRQREF come to the logic "0" (symbols 40, 42, and 43 in FIG. 16). Then, the signal RDYCPU (reverse) rises at the time of T11, stop of the synchronous clock .phi. CPU is released, and the CPU 1 restarts the processing which has been interrupted. The latch circuits 31 to 34 fetch the output signals of the logic gates 28, 29, and 30 and the signal BRQREF respectively when the pulse SAMP equals "1" and latch them while the pulse SAMP equals "0". At the time of T10, only the output of the logic gate 28 is "1" and others are "0" among the signal BRQREF, signal HOLD, and signal BRQDMA. This state is fetched to the latch circuits 31 to 34 while the pulse SAMP equal "1" at the times of T10 and T11 and latched at the time of T1 forward (symbol 37 in FIG. 16).
Because the system and bus use request adjusting apparatus of the existing microcomputer is constituted as described above, the bus use request priority predetermined for each unit cannot be changed or a unit with a low priority cannot use a bus even if the bus is idle while a unit with a high priority obtains the bus use right. Therefore, there is a problem that the bus use efficient is decreased.